Stacked ICs increase device functionality and decrease occupied area by stacking dies vertically. In stacked ICs, a second die is stacked on a first die allowing construction to expand into three dimensions (3D). Stacked ICs allow products with a greater number of components to fit in small form factors. Component density of a semiconductor die is the number of components in the die divided by the die area. For example, stacking a die on an identical die results in approximately double the number of components in the same area to double component density. When a second die is stacked on a first die, the two dies share the same packaging and communicate to external devices through the packaging.
Dies may be stacked using several methods, including Package-on-Package (PoP) processes and through-silicon-stacking (TSS) processes. However, in some applications the height of the stacked IC is restricted. For example, ultra-thin cellular phones may not support stacked ICs having multiple dies. Thus, there is a need to reduce the thickness of stacked ICs.